1. Field of the Invention
The present invention relates to a simulation of a physical system such as an automobile. In particular the present invention relates to a simulation system, method, and article of manufacture in which a continuous simulator and discrete-event simulators are improved by loosely synchronizing the simulators thereby reducing the frequency and cost of inter-thread or inter-processor communication.
2. Description of Related Art
Automobiles in the early years of the 20th century were made up of mechanical parts, including an engine, which is a power source to move the automobile, a brake, an accelerator, a steering wheel, a transmission, and a suspension, and used few electrical mechanisms; exceptions include spark ignition of the engine and a headlight.
Electronic control units (ECUs) have come into use for controlling engines in about the 1970s because of the need for efficiently controlling engines in order to reduce air pollution and in preparation for oil crunch. An ECU typically includes an input interface which converts an analog input signal coming from a sensor to a digital signal, a logic unit (microcomputer) which processes the digital input signal according to a predetermined logic, and an output interface which converts the processed signal to an actuator activation signal.
In addition to mechanical components, electronic components and software form a significant proportion of engine and transmission control systems, Anti-lock Braking Systems (ABSs), Electronic Stability Controls (ESCs), and power steering as well as wiper control and security monitoring systems of today's automobiles. Development costs relating to the electronic components and software are said to be 25 or 40% of the total development cost and make up 70% of the development cost for hybrid electric vehicles.
Electronic control is accomplished by providing multiple ECUs. The ECUs are interconnected through an in-vehicle network, for example a Controller Area Network (CAN). The components such as the engine and transmission which are to be controlled are directly connected to their respective ECUs through wires.
An ECU is a small computer that operates in response to an interrupt from a sensor input and the like. The engine and other components, on the other hand, are continuously mechanically operating. That is, digital systems, which are computer systems, and physical systems, which are mechanical systems, are cooperating simultaneously in the single system of the automobile. Naturally, the complexity of software that supports the cooperation is increasing. Therefore, there is demand for implementation of a mechanism that not only separately tests operation of each ECU but also tests multiple ECUs simultaneously.
On the other hand, actuators such as electromagnetic solenoids and motors are driven by signals output from the ECUs. Solenoids are used in an engine injector, the shift control of the transmission, brake valve controls, and door locks.
A conventional technique used for such tests is Hardware In the Loop Simulation (HILS). An environment in which the ECUs of a whole automobile are tested in particular is called Whole Vehicle HILS (Whole Vehicle Hardware In the Loop Simulation). In the whole vehicle HILS, real ECUs are connected to a dedicated hardware device that emulates components, such as an engine and a transmission mechanism in a laboratory, and tests are conducted according to predetermined scenarios. Outputs from the ECUs are input into a monitoring computer and are displayed on a display. A person responsible for the testing checks the outputs displayed on the display for an abnormal operation.
However, HILS involves burdensome preparations because it uses the dedicated hardware device, which needs to be physically connected to each real ECU. Furthermore, when an ECU is replaced with another one for testing, again the ECU needs to be physically connected to the dedicated hardware device, which is time-consuming. Moreover, testing requires actual time since real ECUs are used. Accordingly, testing many scenarios takes huge amounts of time. In addition, the hardware devices for HILS emulations in general are very expensive.
Therefore, more recently a method in which simulations are configured by software without using expensive emulation hardware devices has been made available. In the method, called Software In the Loop Simulation (SILS), all elements such as microcomputers and input/output circuits contained in ECUs as well as control scenarios are all formed by software simulators. This enables test to be conducted without the hardware of the ECUs.
A simulation system for automobile includes continuous simulators and discrete-event simulators. An example of the continuous simulator is a simulator that simulates a mechanical section of an engine. An example of discrete-event simulator is a simulator for an ECU that operates with the timing of a pulse of engine rotation to control the timings of fuel injection and ignition.
An example of continuous simulator that simulates a 4WD is a simulator that repeatedly calculates operation of the vehicle from torque apportioned to each wheel. An example of discrete-event simulator for 4WD is a simulator that operates with pulsed signals at regular intervals of 10 milliseconds, and that simulates an ECU that determines torque to be apportioned to each wheel from a sensor input such as the yaw rate of the vehicle.
In addition to receiving the pulse signal, the discrete-event simulator reads and writes data through an I/O port asynchronously to a time slice of the continuous simulator. Typically, the discrete-event simulator reads and updates data from a sensor.
FIG. 1 illustrates a block diagram of a configuration of a typical conventional discrete-event/continuous simulation system. The discrete-event simulator of the system includes ECU emulators 102, 104 and 106. While the system in practice includes more ECU emulators, only three ECU emulators are depicted for illustrative purposes.
Since the ECU emulators 102, 104 and 106 are substantially identical in function to one another, only the ECU emulator 102 will be described as a representative example. The ECU emulator 102 includes a CPU emulator 102a and a peripheral emulator 102b. The CPU emulator 102a is a module that emulates a logical function of a real ECU.
The peripheral emulator 102b receives a continuous pulse signal from a plant simulator 108, which is a continuous simulator such as an engine simulator, converts the continuous pulse signal to an interrupt event signal, passes the interrupt event signal to the discrete CPU emulator 102a, or converts an interrupt event signal received from the CPU emulator 102a to a continuous pulse signal.
Enclosed in the dashed rectangular blocks in FIG. 1 are individual threads of a simulation program. The individual threads are preferably allocated to individual cores or processors in a multi-core or multiprocessor environment.
FIG. 2 illustrates a timing chart of communications between the ECU emulators 102, 104 and 106 and the plant simulator 108. As can be seen from FIG. 2, the ECU emulator, which is a discrete system, and the plant simulator, which is a continuous system, in the configuration in FIG. 1 are in synchronization with each other at clock intervals.
However, inter-thread communication occurs at every clock pulse because the plant simulator 108 and the ECU emulators 102, 104 and 106 are executed in different threads as can be seen from the dashed blocks in FIG. 1. If the individual threads are assigned to separate cores or processors for parallel execution, inter-processor communication occurs. The inter-thread communication or the inter-processor communication that occurs once every clock interval involves enormous cost, which inhibits improvement of the speed of operation of the simulation system.
Japanese Published Unexamined Patent Application No. 2001-290860 aims to provide a hardware/software cooperative simulator to improve the speed of simulation by finding an unnecessary synchronization process between simulators and reducing the synchronization process, and discloses a simulator including simulation coordinating means for synchronizing CPU simulation means and peripheral circuit simulation means and determination means for determining whether or not to suppress synchronization in the simulation coordinating means, wherein the synchronization in the simulation coordinating means is suppressed according to the determination means.
Japanese Published Unexamined Patent Application No. 8-227367 aims to provide a debugger that uses a fast simulator that ignores all system operations excluding system operations in which design errors are expected to appear to increase the speed of debugging, and discloses a debugger including a bus simulator of a bus providing a signal corresponding to a bus cycle for interconnecting simulators and means for omitting a bus cycle unnecessary for simulation, wherein a CPU bus cycle irrelevant to simulation is omitted or a periodic clock signal is explicitly avoided from being simulated so that only a schedule of the clock signal is generated.
Japanese Published Unexamined Patent Application No. 2004-30228 discloses a simulator including a CPU simulator, one or more peripheral macro-simulators, and synchronous execution control processing unit controlling synchronous execution of these, wherein the peripheral macro-simulator(s) execute simulation based on a terminal signal when the terminal signal, which is input to a terminal on the basis of simulation in the CPU simulator, has changed. The peripheral macro-simulator(s) detect a change in the input terminal signal, registers the changed terminal signal on a terminal signal list 22, and performs simulation only for the registered terminal signal.
Japanese Published Unexamined Patent Application No. 2006-65758 discloses a circuit simulation method, wherein a response function is provided to a first discrete time model generated from circuit data to generate a second discrete time model, an edge timing of a clock and an effective signal value of a signal input into and output from a clock synchronization circuit at the timing are calculated using the second discrete model, and simulation is performed using these.